1. Field of the Invention
The present invention relates to a bit phase synchronizer, and more particularly to a bit phase synchronizer for establishing and maintaining bit phase synchronization of a data signal being input in the form of a bit string.
2. Description of Related Art
Such a bit phase synchronizer is especially applied to a telecommunications system indicated in the ITU-T (International Telecommunication Union) council (ITU-T Recommendations) G.983.1 xe2x80x9cBROADBAND OPTICAL ACCESS SYSTEMS BASED ON PASSIVE OPTICAL NETWORKS (PON).xe2x80x9d The bit phase synchronizer indicated by this council includes a data signal input terminal and a reset pulse input terminal, where after the reset pulse arrives, a bit phase of the data signal in the form of a burst being input to a data signal input terminal is identified and synchronization is established. The bit phase synchronization is achieved by outputting a data signal with such a synchronized bit phase.
The Patent Gazette, Toku-Kai-Hei (laid open Patent No.) 9-162853 discloses a conventional burst bit phase synchronizer. The burst synchronizer disclosed in the Patent Gazette, first of all, over-samples a plurality of received burst data using a high-speed internal clock. Next, the phases of rising and falling edges of the received data are recognized by EXCLUSIVE OR of adjacent data. Further, bit synchronization around a central phase of an eye pattern of received data based on phase information of both edges thereof is established and fixed.
However, a conventional method such as this has a problem in which jitter ability for the received data deteriorates and bit synchronization cannot correspond to the phase change of the received data, when the deformation of the bit term for the received data is large.
It is a primary object of this invention to provide a bit phase synchronizer in which bit synchronization can follow a phase change of received data, even if the deformation of the bit term of the received data is large.
It is a further object to provide a clock generation circuit producing reduced deformation of a clock wave.
It is still another object of this invention to provide a differentiation circuit that is easily IC packaged, in which a differential input buffer to a rectifier circuit is packaged together.
These and other objects are accomplished by the following units. A bit position synchronizer for establishing bit position synchronization of input signals being input in a form of a bit string and outputting as an output signal, includes: a delay circuit for outputting a plurality of delay output signals by delaying the input signals by giving respective different time delays; a selector unit for selecting one of a plurality of outputs obtained from a plurality of delay circuits corresponding to an input selection signal and outputting as the output signal; a detection circuit for detecting a first changing point and a second changing point of the input signals after a reset pulse is input; a second register for storing information for the first changing point as the first changing point number; a third register for storing information for the second changing point as the second changing point number; and the first register for storing an intermediate value calculated based on a changing point number stored in the second register and the third register and outputting the intermediate value to the selector unit as the selection signal.
Further, in the bit position synchronizer of the present invention, a sampling unit samples input signals with a plurality of phases of clock signals, and the outputs thereof pass through a shift register unit having a plurality of stages with a master clock. A selector unit selects one of outputs from each register of the shift register unit, and generates a bit-synchronized output. A changing point detection unit compares outputs from the sampling unit, detects a signal change at adjacent phases, and gives a number indicating such a phase to the first control unit. The first control unit, after initialization by a reset pulse, stores an indication designating the first changing point in the second register unit, stores an indication designating the next changing point in the third register unit, calculates an intermediate value between them, and stores the intermediate value in the first register unit. The second control unit, after initialization, monitors change of outputs indicated by the second and third register units among outputs from a plurality of the shift register units and of outputs from a shift register in a predetermined range including such outputs. The second control unit increases/decreases a value of the second and third register units when the changing point is detected at a phase position succeeding or prior to the shift register indicated by the second and third register unit. The first register unit selects and controls the selector unit corresponding to the stored value.
Further, a bit position synchronizer of the present invention, includes: a sampling unit for sampling the input signals corresponding to a plurality of phases of clock signals, phases of which are different to each other, at a speed faster than a predetermined clock speed of the bit string, and outputting a plurality of corresponding outputs; a plurality of shift register units for passing a plurality of stages corresponding to a master clock at a speed faster than a clock speed of the bit string by receiving a plurality of outputs of the sampling units; a shift register unit for outputting respective outputs of such a plurality of shift registers; a selector unit for selecting one of outputs from a plurality of shift registers corresponding to a selection control signal and outputting as an output signal; a changing point detection unit for comparing a plurality of outputs from the sampling unit with each other and outputting the first indication designating a phase indicating such a signal change when a signal change is detected at adjacent phases among such a plurality of outputs; a selection control unit, including the first register unit for storing the second indication designating one of a plurality of shift registers, for generating a selection control signal corresponding to the value of the second indication stored in the first register unit; the second and third register units for storing the second indication; the first control unit for storing the first indication received from the changing point detection unit at first in the second register unit as the second indication after initialization by a reset pulse, subsequently storing the first indication received from the changing point detection unit in the third register as the second register, calculating an intermediate value between such two second indications, and storing such a value in the first register unit as the second indication; the second control unit for receiving an output from a plurality of shift registers after initialization by the reset pulse, monitoring change of outputs indicated by the second indication stored in the second and third register units among outputs from a plurality of the shift register units and outputs from a shift register in a first predetermined range including the outputs, and controlling the first, second, and third register units, in which the second control units, when a changing point is detected in outputs from a shift register, a phase position of which is prior to a shift register indicated in a second indication stored in the second and third register units, decreases a value of the second indication stored in the first, second, and third register units and, when a changing point is detected in outputs from a shift register, a phase position of which is subsequent to a shift register indicated in a second indication stored in the second and third register units, increases a value of the second indication stored in the first, second, and third register units. comparison unit for comparing outputs from a plurality of shift registers with a value of the second indication stored in the first register unit, monitoring change of outputs indicated by the second indication stored in the first register unit and of outputs from a shift register in the second predetermined range including the outputs, and controlling the first, second, and third register units. The comparison unit, when a changing point is detected in outputs from a shift register a phase position of which is prior to a shift register indicated in a second indication stored in the first register unit, decreases a value of the selection control signal and, when a changing point is detected in outputs from a shift register, a phase position of which is subsequent to a shift register indicated in a second indication stored in the first register unit, increases a value of the selection control signal.
The second control unit may be composed so as to respond to a slower clock than the master clock.
Further, in accordance with present invention, the structure can be formed in such a way that the first control unit, after initialization, when it is detected that the difference between values of consecutive first indications is lower than 1 bit term, stores the first indication designating a rising phase for the change of the detected signals in the second register unit as the second indication. In addition, the structure can also be formed in such a way that the first control unit also stores the first indication designating a falling phase in the third register as the second indication. Further, the structure can be formed in such a way that the second control unit compares and controls the change of the rising phase by the second indication stored in the second register unit and the change of the falling phase by the second indication stored in the third register unit.